1. Field of the Invention
The present invention is directed to a semiconductor memory device and a method for manufacturing the same, and more particularly to a semiconductor memory device enabling a reduction of a memory cell in size and a method for manufacturing the same.
2. Description of the Related Art
Since unit cell of DRAM(Dynamic Random Access Memory) basically consists of one transistor and one capacitor, there is benefit that an area occupying the unit cell thereof is small. For manufacturing such DRAM, should be performed four-times polysilicon deposition process; a first polysilicon deposition process for a word line, a second polysilicon deposition process for a bit line, a third polysilicon deposition process for a storage node of a capacitor and a fourth polysilicon deposition process for a plate node of the capacitor. Therefore, the manufacturing process of the DRAM is complicated. Further, a read access port and a write access port both are connected to one data line, so an operation of the DRAM as a logic device is complicated.
In order to remove the above mentioned drawbacks, a method for manufacturing the DRAM by one-step polysilicon deposition process had been proposed.
In FIG. 1, DRAM has a pass transistor for writing, a pass transistor for reading, a storage transistor, a capacitor, word lines for driving the pass transistors and bit lines intersecting the word lines for a data-in and data- out. M1 represents the pass transistor for writing, M2 the storage transistor and M3 the pass transistor for reading. Word line WL1 for reading is connected to a gate of the read pass transistor M3. Word line WL2 for writing is connected to a gate of the write pass transistor M1. Bit line BL1 for writing is connected to a source of the write pass transistor M1. Bit line BL2 for reading is connected to a source of the read pass transistor M3. A drain of the write pass transistor M1 is connected to a gate of the storage transistor M2. A drain of the storage transistor M2 is connected to a drain of the read pass transistor M3. A source of the storage transistor is connected to a Vss voltage terminal. A parasitic capacitor C1 is formed between the drain of the write pass transistor and the gate of the storage transistor. As a capacitance of the capacitor C1 is increased, an amount of data stored in DRAM is increased.
A semiconductor memory device including a circuit of FIG. 1 is designed to determine that if Vss voltage level is detected through the bit line, data is stored in the DRAM cell or if the voltage level over Vss voltage level is detected, no data is in the DRAM cell.
In writing operation, the write word line WL2 is accessed and the write pass transistor M1 is turned on. Accordingly, data at the write bit line BL1 is, through the write pass transistor M1, stored in the capacitor C1.
In reading operation, the read word line WL1 is accessed and the read pass transistor M2 is turned on. The storage transistor M2 is turned on or off in response to data stored in the capacitor C1. If data is previously stored in the capacitor C1, the storage transistor C1 is turned on and the Vss voltage level is detected at the read bit line BL2. Otherwise, if no data is stored in the capacitor C1, the storage transistor M2 is turned off and the voltage level over Vss voltage level is sensed at the read bit line BL2.
FIG. 2 is a view showing a layout of DRAM in FIG. 1. Y1 and Y2 each represents DRAM cell unit area. A1 stands for a first active region on which the storage transistor M2 and the read pass transistor M3 are formed. A2 stands for a second active region on which the write pass transistor M3 is formed. 4A indicates a gate of the write pass transistor M1, 4B a gate of the storage transistor M2 and 4C a gate of the read pass transistor M3. Particularly, a width of the gate of the storage transistor M2 is proportional to the capacitance of the capacitor C1, so the width of the gate of the storage transistor M2 is designed larger than that of gates of the read pass transistor M3 and the write pass transistor M1. The reference 2 designates an element separating region isolating the first active region and the second active region. The reference 5 indicates both side portions of the gates 4A, 4B and 4C in the active regions A1, A2. C-1 is a contact hole between the source of the read pass transistor M3 and the read bit lines WL1. C-2 is a contact hole between the source of the storage transistor M2 and the Vss voltage terminal. C-3 is a contact hole between the source of the write pass transistor M1 and the bit line BL1. C-4 is a contact hole between the gate of the storage transistor M2 and the drain of the write pass transistor M1.
FIG. 3 is a sectional view along III-IIIxe2x80x2 of FIG. 2. With reference to FIG. 3, a method for manufacturing DRAM as shown in FIG. 1 and FIG. 2 will be explained.
A device isolating region 2 for separating the first active region A1 and the second active region A2 is formed on a part of the semiconductor substrate 1. A gate oxide and polysilicon are successively deposited over the substrate 1, and then patterned in a known etching method to form gate oxides 3A, 3B, 3C and gates 4A, 4B, 4C. As mentioned above, a width of the gate 4B of the storage transistor M2 is larger than those of the gates 4A, 4C of the other transistors M1, M3. Thereafter, N type of impurity ions are implanted to the substrate on which the gates are formed, forming junction regions 5-1, 5-2, 5-3, 5-4, 5-5 of the respective transistor. The junction region 5-2 is a common junction region of the storage transistor M2 and the read pass transistor M3.
An insulating interlayer 6 provided with contact holes C-1, C-2, C-3 exposing the junction regions 5-1, 5-3, 5-5, is formed on the resultant having the transistors M1, M2, M3. Thereafter, metal wires 7-1, 7-2, 7-3 contacting with the junction regions via contact holes are formed.
As known from the above, in order to produce the DRAM having three transistors as shown in FIG. 2, four-contacts holes C-1, C-2, C-3, C-4 should be required. Accordingly, area for such DRAM is increased, so an integrated density of the semiconductor device is degraded.
Further, since a pitch between the metal wires 7-1, 7-2, 7-3 is smaller and smaller with the high integrated density of the semiconductor device, a reliability of the semiconductor device is debased.
Accordingly, an object of the present invention is to provide a semiconductor device improving a reliability thereof, with satisfying a high integrated density thereof and a method for manufacturing the same.
A semiconductor memory device according to a view of the present invention so as to accomplish the object of the present invention, comprises a first word line, a second word line, a first bit line, a second bit line and a first passer for passing a data loaded on the first bit line by a turn-on thereof when the first word line is accessed. The semiconductor memory device further has a storage for storing a data outputted from the first passer, a second passer for transferring a data stored in the storage to the second bit lines by turn-on thereof when the second word line is accessed and a supplier for providing a substrate voltage for the storage.
In an embodiment, the first word line and the second word line are respectively for writing and reading. The first bit line and the second bit line are respectively for writing and reading. The first passer includes a NMOS transistor and the supplier includes a NMOS transistor with P type of impurity region. The second passer and the storage each has NMOS transistor. In detail, a gate, a source and a drain of the first passer are respectively connected to the write word line, the write bit line and gate of the storage. A gate, a source and a drain of the second passer are respectively connected to the read word line, the read bit line and a drain of the storage. A source of the storage is connected to a source of the supplier. A gate of the supplier is connected to the write word line. The P type of impurity region is formed on a part of the drain of the supplier and is furnished with the substrate voltage. A capacitor is formed between the drain of the first passer and the gate of the storage.
A semiconductor memory device according to another view of the present invention so as to accomplish the object of the present invention, comprises a first active region of first conductivity type having a body disposed at a center of a region defined by four-unit cells area adjacent thereto and branches disposed and extending from the body to respective unit cell area, a second active region of the first conductivity type separated from the first active region by a selected distance and disposed over the two-unit cells area adjacent thereto and a depletion region of the second conductivity formed in the body. A substrate electrode region is disposed at a center of the depletion region. Also, the semiconductor memory device includes a storage formed on the branch of the first active region, a first passer formed on the branch of the first active region and connected to the storage, a supplier formed on the depletion region with the substrate electrode region, for providing a substrate voltage for the storage through the substrate electrode region and a second passer formed on the second active region and connected to the storage. Here, the first conductivity type is P type and the second conductivity is N type.
In an embodiment, the first passer is of a transistor with a gate across the first active region and a drain and a source of second conductivity type both formed at the first active region disposed at sides of the gate thereof. The supplier is of a transistor having a gate across the depletion region and a drain and a source of second conductivity type both formed at the depletion region disposed at sides of the gate thereof. In a part of either source or drain of the depletion region is disposed the substrate electrode region formed by implanting first type of impurity ions. The second passer is of a transistor with a gate across the second active region and a drain and a source of the second conductivity type both formed at the second active region disposed at sides of the gate thereof. The storage is of a transistor having a gate disposed and extending from the first active region to the second active region and a drain and a source of the second conductivity type both formed at the first active region disposed at sides of the gate thereof. The drain of the first passer and the drain of the storage are common. A width of the gate of the storage is larger than those of gates of the first and second passers.
In another embodiment, the gate of the second passer is integrated with the gate of the supplier.
According to still another view of the present invention so as to accomplish the object of the present invention, is provided a substrate having a first active region of the first conductivity type and a second active region of the same conductivity type both isolated from each other. A depletion region of the second conductivity type is formed in a part of the first active region. A first passer and a storage are formed on the first active region, a second passer is formed on the second active region and on the depletion region is formed a supplier, providing a substrate voltage for the storage. An insulating layer is formed on the resultant in which the first and second passers, the storage and the supplier are provided. Etching of the insulating is performed to form a first contact hole exposing a portion of the first passer, a second contact hole exposing a portion of the second passer and a third contact hole exposing another portion of the second passer together with a portion of the storage. Thereafter a first metal wire, a second metal wire and a third metal wire filling the first contact hole, the second contact hole and the third contact hole respectively are formed. A step of forming the first passer, second passer, the storage and the supplier comprises the steps of forming gate insulating layers and gates thereof, forming drains and sources thereof by implanting the first type of impurity ions to the first active region including the depletion region and the second active region and forming a substrate electrode region connected to a substrate voltage by implanting the first conductivity type of impurity ions to a portion of either drain or source of the supplier formed on the depletion region. Between the step of forming the first and second passer, the supplier and the storage and the step of forming the insulating layer, a silicide is formed on the gates, drains and sources of the first passer, the second passer, the supplier and the storage.
In DRAM with a write pass transistor, a read pass transistor and the storage transistor, in order to connect the source of the storage to the Vss voltage terminal without affecting the operation of DRAM, is provided a depletion transistor connected to the storage transistor, the write pass transistor and the substrate voltage. An impurity region of same conductivity to that of a substrate on which DRAM is formed, is formed in either drain or source of the depletion transistor, providing the substrate voltage for the source of the storage without additionally separate electrode. Is required no area for the contact hole through which the storage transistor is connected to the Vss voltage terminal, so the high integrated density can be accomplished. In addition, since the number of contact holes in DRAM of the present invention in comparison with the prior art, the pitch between the metal wires filling the contact holes is relatively larger and therefore a debasement of reliability of the semiconductor device can be reduced.